LogReg.h

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// LogReg.h:
// -------------------
//

#ifndef __IPSDKUTIL_INSTRUCTIONSET_ARITHMETIC_DETAIL_COMMON_LOGREG_H__
#define __IPSDKUTIL_INSTRUCTIONSET_ARITHMETIC_DETAIL_COMMON_LOGREG_H__

#include <IPSDKUtil/IPSDKUtilExports.h>
#include <IPSDKUtil/InstructionSet/RegMaskType.h>
#include <IPSDKUtil/InstructionSet/RegType.h>
#include <IPSDKUtil/InstructionSet/Arithmetic/detail/AddReg.h>
#include <IPSDKUtil/InstructionSet/Arithmetic/detail/FrexpReg.h>
#include <IPSDKUtil/InstructionSet/Arithmetic/detail/MaxReg.h>
#include <IPSDKUtil/InstructionSet/Arithmetic/detail/MulReg.h>
#include <IPSDKUtil/InstructionSet/Arithmetic/detail/SubReg.h>
#include <IPSDKUtil/InstructionSet/Arithmetic/detail/PolynomReg.h>
#include <IPSDKUtil/InstructionSet/Comparison/detail/IsEqualReg.h>
#include <IPSDKUtil/InstructionSet/Comparison/detail/IsLessReg.h>
#include <IPSDKUtil/InstructionSet/Comparison/detail/IsNotEqualReg.h>
#include <IPSDKUtil/InstructionSet/detail/AssignReg.h>
#include <IPSDKUtil/InstructionSet/detail/CastReg.h>
#include <IPSDKUtil/InstructionSet/Logical/detail/BitwiseAndReg.h>
#include <IPSDKUtil/InstructionSet/Logical/detail/IfElseReg.h>
#include <IPSDKUtil/Tools/ForceInline.h>

namespace ipsdk {
namespace simd {
namespace detail {


template <eInstructionSet::domain IS, eInstructionSet::domain ISFma>
struct LogReg<IS, ISFma, ipReal32>
{
    static IPSDK_FORCEINLINE
    typename RegType<IS, ipReal32>::Type
    act(const typename RegType<IS, ipReal32>::Type& in)
    {
        typename RegType<IS, ipReal32>::Type out;
        act(in, out);
        return out;
    }

    static IPSDK_FORCEINLINE
    void
    act(const typename RegType<IS, ipReal32>::Type& in,
        typename RegType<IS, ipReal32>::Type& out)
    {
        typedef typename RegType<IS, ipReal32>::Type RegReal32;
        typedef typename RegMaskType<IS, ipReal32>::Type RegMaskReal32;
        typedef typename RegType<IS, ipInt32>::Type RegInt32;

        const ipInt32 scalarMinNormPos = 0x00800000;
        RegReal32 minNormPos;
        AssignReg<IS, ipReal32>::act(minNormPos, *reinterpret_cast<const ipReal32*>(&scalarMinNormPos));

        RegReal32 x = in;
        MaxReg<IS, ipReal32>::act(x, minNormPos, x); /* cut off denormalized stuff */

        RegInt32 eInt32;
        FrexpReg<IS, ipReal32>::act(x, x, eInt32);
        RegReal32 e;
        CastReg<IS, ipInt32, ipReal32>::act(eInt32, e);

        RegReal32 one, cephesSqrtHalf;
        AssignReg<IS, ipReal32>::act(one, 1.0f);
        AssignReg<IS, ipReal32>::act(cephesSqrtHalf, 0.707106781186547524f);

        /* part2:
        if( x < SQRTHF ) {
        e -= 1;
        x = x + x - 1.0;
        } else { x = x - 1.0; }
        */
        RegReal32 regFromMask, tmp, oneAndMask;
        RegMaskReal32 mask;
        IsLessReg<IS, ipReal32>::act(x, cephesSqrtHalf, mask);
        CastReg<IS, ipReal32, ipReal32>::act(mask, regFromMask);
        BitwiseAndReg<IS, ipReal32>::act(x, regFromMask, tmp);
        SubReg<IS, ipReal32>::act(x, one, x);
        BitwiseAndReg<IS, ipReal32>::act(one, regFromMask, oneAndMask);
        SubReg<IS, ipReal32>::act(e, oneAndMask, e);
        AddReg<IS, ipReal32>::act(x, tmp, x);

        RegReal32 x2;
        MulReg<IS, ipReal32>::act(x, x, x2);

        RegReal32 y;
        PolynomReg<IS, ISFma, 8, ipReal32>::act(
            x,
            +3.3333331174E-1f,          // cephes_log_p8
            -2.4999993993E-1f,          // cephes_log_p7
            +2.0000714765E-1f,          // cephes_log_p6
            -1.6668057665E-1f,          // cephes_log_p5
            +1.4249322787E-1f,          // cephes_log_p4
            -1.2420140846E-1f,          // cephes_log_p3
            1.1676998740E-1f,           // cephes_log_p2
            -1.1514610310E-1f,          // cephes_log_p1
            7.0376836292E-2f,           // cephes_log_p0
            y);

        RegReal32 cephesLogQ1, halfOne, cephesLogQ2;
        AssignReg<IS, ipReal32>::act(cephesLogQ1, -2.12194440e-4f);
        AssignReg<IS, ipReal32>::act(halfOne, .5f);
        AssignReg<IS, ipReal32>::act(cephesLogQ2, 0.693359375f);

        MulReg<IS, ipReal32>::act(y, x, y);
        MulReg<IS, ipReal32>::act(y, x2, y);

        MulReg<IS, ipReal32>::act(e, cephesLogQ1, tmp);
        AddReg<IS, ipReal32>::act(y, tmp, y);

        MulReg<IS, ipReal32>::act(x2, halfOne, tmp);
        SubReg<IS, ipReal32>::act(y, tmp, y);

        MulReg<IS, ipReal32>::act(e, cephesLogQ2, tmp);
        AddReg<IS, ipReal32>::act(x, y, x);
        AddReg<IS, ipReal32>::act(x, tmp, tmp);
  
        RegReal32 inf, minusInf, minusEps, eps, nan;
        RegMaskReal32 inIsNull, inIsNeg, inIsNan, inIsInf;
        AssignReg<IS, ipReal32>::act(inf, std::numeric_limits<ipReal32>::infinity());
        AssignReg<IS, ipReal32>::act(minusInf, -std::numeric_limits<ipReal32>::infinity());
        AssignReg<IS, ipReal32>::act(nan, std::numeric_limits<ipReal32>::quiet_NaN());
        AssignReg<IS, ipReal32>::act(eps, std::numeric_limits<ipReal32>::min());
        AssignReg<IS, ipReal32>::act(minusEps, -std::numeric_limits<ipReal32>::min());
        IsLessReg<IS, ipReal32>::act(in, eps, inIsNull);
        IsLessReg<IS, ipReal32>::act(in, minusEps, inIsNeg);
        IsEqualReg<IS, ipReal32>::act(in, inf, inIsInf);
        IsNotEqualReg<IS, ipReal32>::act(in, in, inIsNan);
        IfElseReg<IS, ipReal32>::act(inIsNull, minusInf, tmp, tmp);
        IfElseReg<IS, ipReal32>::act(inIsNeg, nan, tmp, tmp);
        IfElseReg<IS, ipReal32>::act(inIsInf, inf, tmp, tmp);
        IfElseReg<IS, ipReal32>::act(inIsNan, nan, tmp, out);
    }
};


} // end of namespace detail
} // end of namespace simd
} // end of namespace ipsdk

#endif // __IPSDKUTIL_INSTRUCTIONSET_ARITHMETIC_DETAIL_COMMON_LOGREG_H__