ExpReg.h

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// ExpReg.h:
// -------------------
//

#ifndef __IPSDKUTIL_INSTRUCTIONSET_ARITHMETIC_DETAIL_COMMON_EXPREG_H__
#define __IPSDKUTIL_INSTRUCTIONSET_ARITHMETIC_DETAIL_COMMON_EXPREG_H__

#include <IPSDKUtil/IPSDKUtilExports.h>
#include <IPSDKUtil/InstructionSet/RegMaskType.h>
#include <IPSDKUtil/InstructionSet/RegType.h>
#include <IPSDKUtil/InstructionSet/Arithmetic/detail/AddReg.h>
#include <IPSDKUtil/InstructionSet/Arithmetic/detail/FloorReg.h>
#include <IPSDKUtil/InstructionSet/Arithmetic/detail/MaxReg.h>
#include <IPSDKUtil/InstructionSet/Arithmetic/detail/MinReg.h>
#include <IPSDKUtil/InstructionSet/Arithmetic/detail/MulReg.h>
#include <IPSDKUtil/InstructionSet/Arithmetic/detail/SubReg.h>
#include <IPSDKUtil/InstructionSet/Arithmetic/detail/PolynomReg.h>
#include <IPSDKUtil/InstructionSet/Comparison/detail/IsEqualReg.h>
#include <IPSDKUtil/InstructionSet/detail/AssignReg.h>
#include <IPSDKUtil/InstructionSet/detail/BitwiseCastReg.h>
#include <IPSDKUtil/InstructionSet/detail/CastReg.h>
#include <IPSDKUtil/InstructionSet/Logical/detail/IfElseReg.h>
#include <IPSDKUtil/InstructionSet/Logical/detail/ShiftLeftReg.h>
#include <IPSDKUtil/InstructionSet/Logical/detail/ShiftRightReg.h>
#include <IPSDKUtil/Tools/ForceInline.h>

#include <limits>

namespace ipsdk {
namespace simd {
namespace detail {


template <eInstructionSet::domain IS, eInstructionSet::domain ISFma>
struct ExpReg<IS, ISFma, ipReal32>
{
    static IPSDK_FORCEINLINE
    typename RegType<IS, ipReal32>::Type
    act(const typename RegType<IS, ipReal32>::Type& in)
    {
        typename RegType<IS, ipReal32>::Type out;
        act(in, out);
        return out;
    }

    static IPSDK_FORCEINLINE
    void
    act(const typename RegType<IS, ipReal32>::Type& in,
        typename RegType<IS, ipReal32>::Type& out)
    {
        typedef typename RegType<IS, ipReal32>::Type RegReal32;
        typedef typename RegMaskType<IS, ipReal32>::Type RegMaskReal32;
        typedef typename RegType<IS, ipInt32>::Type RegInt32;

        RegReal32 x = in;

        RegReal32 tmp, fx;
        AssignReg<IS, ipReal32>::act(tmp, .0f);

        RegReal32 one;
        AssignReg<IS, ipReal32>::act(one, 1.0f);

        RegReal32 expHi, expLo;
        AssignReg<IS, ipReal32>::act(expHi, 88.3762626647949f);
        AssignReg<IS, ipReal32>::act(expLo, -88.3762626647949f);

        MinReg<IS, ipReal32>::act(x, expHi, x);
        MaxReg<IS, ipReal32>::act(x, expLo, x);

        /* express exp(x) as exp(g + n*log(2)) */
        RegReal32 log2EF, halfOne;
        AssignReg<IS, ipReal32>::act(log2EF, 1.44269504088896341f);
        AssignReg<IS, ipReal32>::act(halfOne, 0.5f);

        MulReg<IS, ipReal32>::act(x, log2EF, fx);
        AddReg<IS, ipReal32>::act(fx, halfOne, fx);

        FloorReg<IS, ipReal32>::act(fx, fx);

        RegReal32 cephesExpC1, cephesExpC2, z;
        AssignReg<IS, ipReal32>::act(cephesExpC1, 0.693359375f);
        AssignReg<IS, ipReal32>::act(cephesExpC2, -2.12194440e-4f);
        MulReg<IS, ipReal32>::act(fx, cephesExpC1, tmp);
        MulReg<IS, ipReal32>::act(fx, cephesExpC2, z);
        SubReg<IS, ipReal32>::act(x, tmp, x);
        SubReg<IS, ipReal32>::act(x, z, x);

        MulReg<IS, ipReal32>::act(x, x, z);
        PolynomReg<IS, IS, 5, ipReal32>::act(
            x,
            +5.0000001201E-1f,          // cephes_exp_p5
            +1.6666665459E-1f,          // cephes_exp_p4
            +4.1665795894E-2f,          // cephes_exp_p3
            +8.3334519073E-3f,          // cephes_exp_p2
            +1.3981999507E-3f,          // cephes_exp_p1
            +1.9875691500E-4f,          // cephes_exp_p0
            tmp);
        MulReg<IS, ipReal32>::act(tmp, z, tmp);
        AddReg<IS, ipReal32>::act(tmp, x, tmp);
        AddReg<IS, ipReal32>::act(tmp, one, tmp);

        /* build 2^n */
        RegInt32 emm0;
        CastReg<IS, ipReal32, ipInt32>::act(fx, emm0);
        RegInt32 Reg127;
        AssignReg<IS, ipInt32>::act(Reg127, 127);
        AddReg<IS, ipInt32>::act(emm0, Reg127, emm0);
        ShiftLeftReg<IS, ipInt32>::act(emm0, 23, emm0);
        RegReal32 pow2n;
        BitwiseCastReg<IS, ipInt32, ipReal32>::act(emm0, pow2n);

        MulReg<IS, ipReal32>::act(tmp, pow2n, tmp);

        // test particular values:
        // - if in equals to infinity, out must equal to infinity
        RegReal32 infinity;
        AssignReg<IS, ipReal32>::act(infinity, std::numeric_limits<ipReal32>::infinity());
        RegMaskReal32 inEqualsToInfinity;
        IsEqualReg<IS, ipReal32>::act(in, infinity, inEqualsToInfinity);
        IfElseReg<IS, ipReal32>::act(inEqualsToInfinity, infinity, tmp, tmp);

        // - if in equals to NaN, out must equal to Nan
        RegReal32 nan;
        RegMaskReal32 inIsNotNaN;
        AssignReg<IS, ipReal32>::act(nan, std::numeric_limits<ipReal32>::quiet_NaN());
        // in is different from nan if and only if (in == in) is true
        IsEqualReg<IS, ipReal32>::act(in, in, inIsNotNaN);
        IfElseReg<IS, ipReal32>::act(inIsNotNaN, tmp, nan, out);
    }
};


} // end of namespace detail
} // end of namespace simd
} // end of namespace ipsdk

#endif // __IPSDKUTIL_INSTRUCTIONSET_ARITHMETIC_DETAIL_COMMON_EXPREG_H__